SPICE Model
PDK
Standard Cell
Design Environment
Circuit SimulationCircuit Analysis
Circuit SimulationStandard Cell
Design & Verification
Parametric Testing
Noise Measurement
Integrated Testing
High Performance FastSPICE Simulator
Its dual-solver engine boosts the simulation throughput of all modern complex designs, including memory (DRAM, SRAM, Flash, MRAM), FPGA, custom digital, and SoC circuits
With the breakthrough FastSPICE algorithm, intelligent topology recognition, and automatic partition technology, NanoSpice Pro delivers superior performance and capacity to address advanced node verification challenges
Adaptive dual-solver technology, i.e., seamless integration of the state-of-the-art digital engine and the giga-scale analog engine, ensures superior analog accuracy and digital performance for mixed-signal designs
NanoSpice Pro provides a unique one-stop memory simulation solution to meet all needs for memory cell design, memory array and compiler verification, memory characterization, and full-chip verification with up to 10X+ performance increase over other commercial simulators
Intelligent topology recognition &
automatic partitioning
Up to 10X+ faster
simulation throughput
Advanced RC reduction
fast yet accurate model evalsuation
Superior analog accuracy &
digital performance
Intelligent circuit partitioning algorithm eliminating local option settings for usability enhancement
Multi-process support, post-simulation DSPF
back-annotation check, SOA/circuit inspection, etc.
Memory circuit full chip timing/power/function verification
SRAM/DRAM/Flash/etc.
Transistor-level simulation verification
of custom digital circuits
SOC
full-chip
verification
Full-chip
mixed-signal
simulation
